gFdZddlmZddlZddlmZddlmZddlm Z m Z Gdd ej ej Z dS) zYShared helper utility for mapping classical resources from one circuit or DAG to another.) annotationsN)Bit)expr)ClassicalRegisterClbitcneZdZdZdZ dddd d Zd!dZdddZdZd"dZ dZ dZ dZ dZ dZdZdS)#VariableMapperaStateful helper class that manages the mapping of variables in conditions and expressions. This is designed to be used by both :class:`.QuantumCircuit` and :class:`.DAGCircuit` when managing operations that need to map classical resources from one circuit to another. The general usage is to initialise this at the start of a many-block mapping operation, then call its :meth:`map_condition`, :meth:`map_target` or :meth:`map_expr` methods as appropriate, which will return the new object that should be used. If an ``add_register`` callable is given to the initializer, the mapper will use it to attempt to add new aliasing registers to the outer circuit object, if there is not already a suitable register for the mapping available in the circuit. If this parameter is not given, a ``ValueError`` will be raised instead. The given ``add_register`` callable may choose to raise its own exception.) target_cregs register_mapbit_mapvar_map add_registerN)rr "typing.Iterable[ClassicalRegister]r typing.Mapping[Bit, Bit]r)typing.Mapping[expr.Var, expr.Var] | Noner1typing.Callable[[ClassicalRegister], None] | Nonecjt||_i|_||_|pi|_||_dSN)tupler r r rr)selfr r rrs \/granary/edev/quantum/lib/python3.11/site-packages/qiskit/circuit/_classical_resource_map.py__init__zVariableMapper.__init__*s<",// }" (theirsrreturncRj|jx}|Sfd|D}jD]}|t |kr|}nEjt d|jdt|}||j|j<|S)z}Map the target's registers to suitable equivalents in the destination, adding an extra one if there's no exact match.Nc*g|]}j|Sr .0bitrs r z0VariableMapper._map_register..=s ;;;St|C(;;;r Register '(' has no counterpart in the destination.bits)r getnamer listr ValueErrorr)rr mapped_theirs mapped_bitsourss` r _map_registerzVariableMapper._map_register8s".226;?? ?M L ;;;;F;;; % - -Dd4jj(( $ ) ( !cfk!c!c!cddd-;???M   m , , ,)6&+&rF) allow_reorderc |dSt|tjr|S|\}}t|trj||fS|s||fSfd|D}t|}jD]}|t|kr|}nKj  d|j dt|} |dt|D |dt|dddd  td  fd |Dddd d } || fS) aMap the given ``condition`` so that it only references variables in the destination circuit (as given to this class on initialization). If ``allow_reorder`` is ``True``, then when a legacy condition (the two-tuple form) is made on a register that has a counterpart in the destination with all the same (mapped) bits but in a different order, then that register will be used and the value suitably modified to make the equality condition work. This is maintaining legacy (tested) behavior of :meth:`.DAGCircuit.compose`; nowhere else does this, and in general this would require *far* more complex classical rewriting than Terra needs to worry about in the full expression era. Nc*g|]}j|Srr r!s rr$z0VariableMapper.map_condition..as AAA3T\#.AAArr%r&r'ci|]\}}|| Srr)r"ir#s r z0VariableMapper.map_condition..nsGGG3S!GGGr0bc34K|]}|VdSrr)r"r# new_order value_bitss r z/VariableMapper.map_condition..ps,"W"W#:in#="W"W"W"W"W"Wr) isinstancerExprmap_exprrr r0setr rexc_typer*r enumeratelenintjoin) r conditionr1targetvaluemapped_bits_ordermapped_bits_setregisterr- mapped_valuer<r=s ` @@r map_conditionzVariableMapper.map_conditionJs  4 i + + ,==++ +!  fe $ $ 1L(%0 0 7&&v..6 6BAAA&AAA/00) - -H#h--// ( 0 (mmVVVV.3DEEEM   m , , ,GG)4E*F*FGGG /F ////"5 277"W"W"W"W"W"W"W"WWWX\X\Z\X\]_`aa |,,rct|tr |j|St|tr||S||S)zMap the real-time variables in a ``target`` of a :class:`.SwitchCaseOp` to the new circuit, as defined in the ``circuit`` argument of the initializer of this class.)r@rr rr0rB)rrJs r map_targetzVariableMapper.map_targetss\ fe $ $ (<' ' f/ 0 0 .%%f-- -}}V$$$rnode expr.Exprc,||S)zEMap the variables in an :class:`~.expr.Expr` node to the new circuit.)acceptrrSs rrBzVariableMapper.map_expr|s{{4   rcXt|jtr*tj|j|j|jSt|jtr2tj||j|jS|j ||Sr) r@varrrVarr typerr0rr)rWs r visit_varzVariableMapper.visit_vars dh & & ?8DL2DI>> > dh 1 2 2 E8D..tx88$)DD D|d+++rc@tj|j|jSr)rValuerKr[rWs r visit_valuezVariableMapper.visit_valuesz$*di000rcrtj|j|j||jSr)rUnaryopoperandrVr[rWs r visit_unaryzVariableMapper.visit_unarys*z$'4<#6#6t#<#{47DI$4$4T$:$:DJB ) KO ) ) ) ) ) )$r|s`_"""""" 77777777|X|X|X|X|XT%di0|X|X|X|X|Xr